1. Technical Field
The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly, to a semiconductor device having box-shaped cylindrical storage nodes and a method of fabricating the same.
2. Description of the Related Art
A semiconductor memory device, particularly, a dynamic random access memory (DRAM) device is a memory device for storing data in a unit cell. That is, the unit cell of such a DRAM includes one access transistor and one cell capacitor, which are connected in series. As the integration of such a DRAM is increased, the area of the unit cell is significantly reduced, and thus, the capacitance of the capacitor is also decreased. However, the reduced capacitance of the capacitor negatively impacts the capability to store data. Thus, it may occur that a device having a low capacitance could fail to correctly read the data stored in advance. Therefore, in order to obtain a high performance DRAM device, the capacitance of the capacitor needs to be increased.
In order to increase the capacitance of such a cell capacitor, technologies for increasing the surface area of a storage node to be used as a lower electrode of the cell capacitor have been widely employed. For example, a cylindrical storage node has been normally employed for such a highly-integrated DRAM.
Such a cylindrical storage node and a fabrication method thereof are disclosed in U.S. Pat. No. 6,329,683 entitled “Semiconductor memory device and manufacturing method thereof which make it possible to improve reliability of cell-capacitor and also to simplify the manufacturing processes” to Yusuke Kohyama.
FIG. 1A is a plan view illustrating a structure of a conventional semiconductor device having cylindrical storage nodes, and FIG. 1B is a cross-sectional view taken along a line of I-I′ of FIG. 1A.
Referring to FIGS. 1A and 1B, a device isolation layer 15 for isolating an active region “A” is disposed inside a semiconductor substrate 10. The active regions A are aligned with and spaced apart from each other at uniform intervals, and each active region A has a major axis L1 and a minor axis L2. A gate insulating layer 20 is disposed on the semiconductor substrate having the device isolation layer 15 formed thereon. Gate electrodes 25 are disposed on the gate insulating layer 20. The gate electrodes 25 are disposed to intersect above the active regions A. A gate protecting layer 30 is disposed on the semiconductor substrate having the gate electrodes 25 formed thereon. Source regions “S” and drain regions “D” are disposed between the gate electrodes 25, inside the active regions. An interlayer insulating layer 40 is disposed to cover the gate protecting layer 30. Buried contact plugs 45 are disposed to penetrate the interlayer insulating layer 40 and to be in contact with the source regions S respectively.
Being in contact with the buried contact plugs 45 respectively, oval-shaped cylindrical storage nodes 55 are disposed to extend upwardly. Although in some drawings, the cylindrical storage nodes in the disclosure of U.S. Pat. No. 6,329,683 may be shown to have a rectangular-shape when viewed from above, because the storage nodes are fabricated by a contact method, even though the initial design shape of the storage node may be rectangular, after fabrication the cylindrical storage nodes have round-shaped (rounded) corners. Therefore, as shown in FIG. 1A, the storage nodes 55 have an oval-shaped cylindrical structure. An etch stop layer 50 is disposed on the interlayer insulating layer 40, between the oval-shaped cylindrical storage nodes 55.
As shown in the drawings, the oval-shaped cylindrical storage nodes 55 are aligned such that a major axis Y1 of each oval-shaped cylindrical storage node is in parallel with the major axis L1 of the active region A. However, the design width of the capacitor is reduced as the integration of the device is increased, and thus, the space for the oval shape of the storage node 55 in the direction of a minor axis Y2 is significantly also reduced. Therefore, a defect such as is shown as B1 in FIG. 1 may occur, in which the oval-shaped space of the storage node 55 in the minor axis Y2 may overlap. Or, a bridge defect may occur, such as is shown as B2 in FIG. 1, in which the interval between neighboring storage nodes is reduced, so that the storage nodes collapse. Therefore, to address these defects, circular-shaped cylindrical storage nodes have been proposed recently instead of the oval-shaped cylindrical storage nodes. However, the surface area of the circular-shaped cylindrical storage nodes is reduced compared with that of the oval-shaped cylindrical storage nodes, thereby decreasing the capacitance of the capacitor. Furthermore, because the conventional storage nodes are fabricated by a contact method, even though the design of the mask is rectangular-shaped during the exposure process, the actual patterns that are formed have round-shaped corners, so that the storage nodes resultingly have a smaller surface area than that of the initially designed patterns. Therefore, there is a need to minimize the defect generation rates due to collapsed storage nodes, while increasing the capacitance of the capacitor within the limited space area.
Accordingly, it would be desirable to provide a semiconductor device suitable to minimizing the defect generation rates due to collapsed storage nodes, while increasing the capacitance of its capacitor within the restricted area, and a method of fabricating the same.
In one aspect of the present invention, a method of fabricating a semiconductor device includes forming an interlayer insulating layer on a semiconductor substrate. Buried contact plugs are formed to penetrate the interlayer insulating layer. A molding layer and a photoresist layer are sequentially formed on the semiconductor substrate having the buried contact plugs formed thereon. Using a first phase shift mask having line-and-space type patterns, the photoresist layer is exposed, thereby forming first exposure regions. Using a second phase shift mask having line-and-space type patterns, the photoresist layer having the first exposure regions is exposed, thereby forming second exposure regions intersecting the first exposure regions. The photoresist layer having the first and the second exposure regions is developed, thereby forming a photoresist pattern having rectangular-shaped openings, and the rectangular-shaped openings are formed at cross points of the first and the second exposure regions. The molding layer is etched using the photoresist pattern as an etch mask, thereby forming storage node holes exposing the buried contact plugs. Storage nodes are formed inside the storage node holes.
After forming the molding layer, the method may further include forming a hard mask layer on the molding layer. The formation of storage node holes may include patterning the hard mask layer using the photoresist pattern, thereby forming a hard mask pattern. Then, the molding layer may be etched using the hard mask pattern as an etch mask, thereby forming storage node holes exposing the buried contact plugs.
The hard mask layer may be formed of a material layer having an etch selectivity relative to the molding layer.
Beneficially, the thickness of the first exposure regions or the second exposure regions is smaller than the thickness of the photoresist layer, and the thickness of the overlapping exposure regions of the first exposure regions and the second exposure regions is the same as the thickness of the photoresist layer.
Beneficially, the pattern intervals of the line-and-space type patterns in the first phase shift mask and the second phase shift mask are the same.
After forming the buried contact plugs, the method may further include forming buffer conductive layer patterns on the semiconductor substrate having the buried contact plugs formed thereon, the buffer conductive layer patterns being in contact with the buried contact plugs and having a wider area. The step of forming the storage node holes may include etching the molding layer using the photoresist pattern as an etch mask, thereby forming storage node holes exposing the buffer conductive layer patterns.
After forming the buried contact plugs, the method may further include forming an etch stop layer on the semiconductor substrate having the buried contact plugs. The step of forming the storage node holes may include sequentially etching the molding layer and the etch stop layer using the photoresist pattern as an etch mask, thereby forming storage node holes exposing the buried contact plugs.
After forming the storage node holes, the method may further include cleaning the inside of the storage node holes using a wet cleaning solution.
In another aspect, the present invention provides a method of fabricating a semiconductor device having box-shaped cylindrical storage nodes. The method includes forming an interlayer insulating layer on a semiconductor substrate. Buried contact plugs are formed to penetrate the interlayer insulating layer. A molding layer, a first hard mask layer, and a second hard mask layer are sequentially formed on the semiconductor substrate having the buried contact plugs formed thereon. The second hard mask layer is patterned, thereby forming line-and-space type upper hard mask patterns. The first hard mask layer is patterned, thereby forming line-and-space type lower hard mask patterns intersecting the upper hard mask patterns. The molding layer is etched using the upper and the lower hard mask patterns as etch masks, thereby forming storage node holes exposing the buried contact plugs. Storage nodes are formed inside the storage node holes.
The pattern intervals of the line-and-space type patterns in the lower hard mask patterns and the upper hard mask patterns may be same.
The first hard mask layer may be formed of a material layer having an etch selectivity relative to the molding layer.
The second hard mask layer may be formed of a material layer having an etch selectivity relative to the molding layer.
The second hard mask layer may be formed of a material layer having an etch selectivity relative to the first hard mask layer.
After forming the buried contact plugs, the method may further include forming buffer conductive layer patterns on the semiconductor substrate having the buried contact plugs formed thereon, and the buffer conductive layer patterns are in contact with the buried contact plugs and are wider than the contact plugs. The step of forming the storage node holes includes etching the molding layer using the upper and the lower hard mask patterns as etch masks, thereby forming storage node holes exposing the buffer conductive layer patterns.
After forming the buried contact plugs, the method may further include forming an etch stop layer on the semiconductor substrate having the buried contact plugs. The step of forming the storage node holes includes sequentially etching the molding layer and the etch stop layer using the upper and the lower hard mask patterns as etch masks, thereby forming storage node holes exposing the buried contact plugs.
After forming the storage node holes, the method may further include cleaning the inside of the storage node holes using a wet cleaning solution.
In yet another aspect, the present invention provides a method of fabricating a semiconductor device having box-shaped cylindrical storage nodes. The method includes forming an interlayer insulating layer on a semiconductor substrate. Buried contact plugs are formed to penetrate the interlayer insulating layer. A molding layer and a hard mask layer are sequentially formed on the semiconductor substrate having the buried contact plugs formed thereon. The hard mask layer is patterned, thereby forming line-and-space type hard mask patterns. A photoresist layer is formed on the semiconductor substrate having the hard mask patterns. The photoresist layer is patterned, thereby forming line-and-space type photoresist patterns intersecting the hard mask patterns. The molding layer is etched using the photoresist patterns and the hard mask patterns as etch masks, thereby forming storage node holes exposing the buried contact plugs. Storage nodes are formed inside the storage node holes.
The pattern intervals of the line-and-space type patterns in the photoresist patterns and the hard mask patterns may be same.
Preferably, the hard mask patterns is formed of a material layer having an etch selectivity relative to the molding layer.
After forming the buried contact plugs, the method may further include forming buffer conductive layer patterns on the semiconductor substrate having the buried contact plugs formed thereon, and the buffer conductive layer patterns are in contact with the buried contact plugs and are wider than the contact plugs. The step of forming the storage node holes includes etching the molding layer using the photoresist patterns and the hard mask patterns as etch masks, thereby forming storage node holes exposing the buffer conductive layer patterns.
After forming the buried contact plugs, the method may further include forming an etch stop layer on the semiconductor substrate having the buried contact plugs. The step of forming the storage node holes includes sequentially etching the molding layer and the etch stop layer using the photoresist patterns and the hard mask patterns as etch masks, thereby forming storage node holes exposing the buried contact plugs.
After forming the storage node holes, the method may further include cleaning the inside of the storage node holes using a wet cleaning solution.
In yet another aspect of the present invention, a semiconductor device is provided having box-shaped cylindrical storage nodes. The semiconductor device includes active regions disposed inside a semiconductor substrate with spaced in uniform intervals. Each active region has a major axis and a minor axis. MOS transistors are disposed on the active regions. An interlayer insulating layer is disposed on the semiconductor substrate having the MOS transistors formed thereon. Are disposed buried contact plugs penetrating the interlayer insulating layer, and being in contact with source regions of the MOS transistors respectively. Box-shaped cylindrical storage nodes are disposed on the buried contact plugs, and each storage node has opposite corners being aligned in parallel with the major axis of the active regions.
Preferably, the box-shaped cylindrical storage nodes have rectangular shapes or rhombus shapes when viewed from the plan view.
The semiconductor device may further include buffer conductive layer patterns on the buried contact plugs. The buffer conductive layer patterns are in contact with the buried contact plugs respectively and are wider than the contact plugs. Box-shaped cylindrical storage nodes having opposite corners being in parallel with the major axes of the active regions are disposed on the buffer conductive layer patterns
Etch stop layers may be disposed on the interlayer insulating layer under the outer sidewalls of the box-shaped cylindrical storage nodes.